Read only memories, generally referred to as nonvolatile memories, have merits of lower power consumption. A read only memory having flat-type memory cells has been proposed in 1988 Symposium on VLSI Circuits, pp.85-86, entitled 16 Mb ROM Design Using Bank Select Architecture, in which data stored in memory cells are read out through an hierarchical bitline structure under the way of bank selection.
FIG. 1 shows a general configuration of memory cell array like that of the article, being coupled with bias circuits. Memory cell array 10 is constructed of a plurality of flat-type memory cells, such as M11, M12, M13, M14 arranged in a NOR logic. The memory cells are connected to main bit lines MBL0-MBL2 through string (or bank) selection transistors ST0-ST4, each of the main bit lines being coupled to a pair of the string selection transistors. The memory cells also are connected to ground lines GBL0-GBL2 through ground selection transistors GT0-GT5, each of the ground lines being coupled to a pair of the ground selection transistors. Gates of the string and ground selection transistors are coupled, respectively, to string selection lines SSL0 and SSL1 and to ground section lines GSL0 and L1. The ground lines and main bit lines are coupled to bias circuits 20 and 30, respectively. Bias circuit 20 receives precharge signal PPRE1 and discharge signal PDIS1 while bias circuit 30 receives precharge signal PPRE2 and discharge signal PDIS2.
In operation, before a sensing cycle for reading, all of the main bit lines including a selected one are discharged and then only a selected main bit line is precharged at a predetermined voltage level in response to PPRE2. Assuming that memory cell M11 is selected for reading, SSL0, GSL0, and wordline WL0 are charged to high levels while all other wordlines and selection lines are held in low levels. Main bitline MBL0 connected to M11 through string selection transistor ST0 is charged to a predetermined voltage level in response to PPRE2. Other main bitlines not selected are held at 0V or in a floating state. The selected ground line GBL0 is set at 0V and other ground lines not selected are held at 0V or in a floating state.
If the selected memory cell M11 has been programmed as an on-cell, a sensing current passes through the channel of M11 and thereby a voltage level on MBL0 is detected by a sense amplifier as a low level. But if the M11 has been programmed as an off-cell, MBL0 maintains the precharged level. However, if adjacent memory cells, e.g., M12, M13, and M14, are all on-cells while M11 is an off-cell, leakage current path A is formed through the adjacent cells to GBL1, causing a failure in reading the selected off-cell M11.
Therefore, there seems a way to obviate such a problem in reading an off-cell. A precharge voltage might be applied to those non-selected main bitlines and ground lines that are adjacent to the selected main bit line and ground line, as well as to the selected main bitline and ground line. As shown in FIG. 2, discharge signals PDIS1 and PDIS2 would be activated in response to ATD (address transition detection) signal SUM, and then precharge signals PPRE1 and PPRE2 would be activated in response to the falling edges of PDIS1 and PDIS2, respectively. But assume that PDIS1 is active later than PDIS2 by time B, due to a difference of propagation skew between PDIS1 and PDIS2 in the device. Then PPRE1 is activated later than PPRE2 by time C. Since a selected main bitline is precharged earlier than a non-selected ground line, there is a capacitive coupling phenomenon between the selected main bitline and non-selected ground line (e.g., MBL0 and GBL1). As a result, the voltage level on the selected main bitline may be over the predetermined precharge voltage level by a level T. This excessive precharge voltage may cause a failure to read the selected memory cell.